A programmable logic device (PLD) is a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. Conventionally, a PLD receives one or more external reference clock signals to generate one or more internal clock signals to operate internal digital circuits. Clock management circuits control timing of various clock signals in the PLD or other integrated circuit device.
When a clock signal propagates through an integrated circuit device, the clock signal can become skewed (delayed) so that signals in one part of the device that were generated from the skewed clock signal are out of phase with signals generated in another part of the device. Clock skew is caused by various factors, such as capacitive and resistive loading on the clock line, causing propagation delay. Clock management circuits can compensate for skewing of a clock signal as the clock signal propagates within or between IC devices.
Clock management circuits can also perform digital frequency synthesis in which a clock signal is generated whose frequency is the frequency of a reference clock signal multiplied by a rational number. For example, the generated clock signal may have a frequency 7/5 of the reference clock frequency. It is important for proper operation of circuits in the integrated circuit device that a generated clock signal be maintained accurately at the specified phase and frequency. This is often done by assuring that the phase of the generated clock signal coincide with that of the reference clock signal when concurrence should occur. For example, if the generated clock frequency is 7/5 of the reference clock frequency, then every 7 cycles of the generated clock signal and every 5 cycles of the reference clock signal, the two clock edges should be in concurrence.
Phase locked loops and delay locked loops compensate for clock skew, bringing the phase of a clock signal in one part of the device into alignment with the clock signal in another part of the device. Delay locked loops use a delay line to manage the propagation delay of the clock signals. Delay lines typically comprise a number of delay elements whose delay may be controlled by controlling either a voltage or the number of delay elements. If the total delay of the delay line is controlled by adjusting the total number of delay elements on the clock path, the delay line may be referred to as a tap-controlled delay line, where taps are taken from the delay line between each of the delay elements.
Due to their relative simplicity, oscillators are sometimes constructed in integrated circuits by feeding back the output of the delay line to its input after an inversion. If the delay line in the oscillator is voltage-controlled, analog circuits adjust the frequency by adjusting the voltage applied to the delay line (voltage controlled oscillators). In an oscillator based on a tap-controlled delay line, the number of delay elements in a delay line is used to control the frequency.
Young and Bauer in U.S. Pat. No. 6,107,826; Hassoun, Goetting and Logue in U.S. Pat. No. 6,289,068; Robinson, Grung, and Chen in U.S. Pat. No. 6,356,160; and Nguyen in U.S. Pat. Nos. 6,255,880 and 6,373,308 describe clock management structures, and these patents are incorporated herein by reference. Logue, Percey, and Goetting in U.S. patent application Ser. No. 09/684,529 describe a “Synchronized Multi-Output Digital Clock Manager” that uses a delay lock loop and digital frequency synthesis for clock signal management. This patent application is also incorporated herein by reference.
Young, Logue, Percey, Goetting, and Ching in U.S. patent application Ser. No. 09/684,540 describe a “Digital Phase Shifter”, also incorporated herein by reference.
Logue in U.S. Pat. No. 6,384,647 describes a “Digital Clock Multiplier and Divider with Synchronization During Concurrences”, also incorporated herein by reference. FIG. 3b of that patent is presented here as FIG. 1.
FIG. 1 herein shows the effect of hard phase alignment. A clock output signal C_O_CLK is generated from a reference clock signal REF_CLK. This generated clock signal C_O_CLK has approximately the desired frequency. In the example of FIG. 1, REF_CLK has a period of 50 units of time. The generated clock signal is four times as fast as the reference clock signal and thus should have a period of 12.50 units of time. But the generated clock signal C_O_CLK actually has a period of only 12 units of time. Therefore C_O_CLK becomes out of phase with REF_CLK. Thus, in a window W when concurrence should occur, instead of continuing to generate C_O_CLK, the generated clock signal is adjusted using the edge of REF_CLK, so C_O_CLK is again synchronized with REF_CLK. This method of synchronizing to the REF_CLK signal is called hard phase alignment.
A phenomenon called jitter randomly causes clock edges to become advanced or retarded. Jitter occurs even to the reference clock signal. Thus, it is difficult to align a generated clock signal to a reference clock signal when both have jitter. If a window is used, and jitter places an edge beyond the window, the clock management circuit may be unable to maintain the synchronization of a generated clock signal to a reference clock signal.
In an IC such as an FPGA in which a wide range of clock frequencies must be offered, the window must be a different size for different user-selected operating frequencies. Typically, the user must specify the window placement during programming of the FPGA. Also, if it is desired to make all generated clock pulses of nearly equal width (reduce jitter), it is necessary to provide a wide range of delays in order to better adjust the generated clock signal continuously, which requires enough chip area to accommodate many delay circuits. Still, the window for alignment must be pre-calculated, and if jitter is too great, the reference clock edge will not arrive during the window, and alignment will not occur. In one circuit, the generated clock signal stopped oscillating in the presence of high jitter, an unacceptable result. Thus there is a need for a phase alignment circuit and method that generates a reliable clock signal in the presence of high jitter and high clock skew. It would be desirable, also, to achieve this result in a small chip area. It is also desirable that the phase alignment circuit contribute a small amount of internal IC noise due to its own switching.